1. Field of the Invention
The invention relates to the field of electrically programmable and electrically erasable memory cells, particularly those fabricated with metal-oxide-semiconductor (MOS) technology and employing floating gates for storing electrical charge.
2. Prior Art
Fabrication of electrically programmable read-only-memories (EPROMs) utilizing metal-oxide-semiconductor (MOS) technology is well-known in the prior art (see U.S. Pat. Nos. 3,660,819; 4,142,926; 4,114,255; and 4,412,310). These EPROMs employ memory cells utilizing floating gates which are generally formed from polysilicon members completely surrounded by an insulator. Electrical charge is transferred into the floating gates using a variety of mechanisms such as avalanche injection, channel injection, Fowler-Nordheim tunnelling, channel hot electron injection, etc. A variety of phenomena have been used to remove charge from the floating gate, including exposing the memory to ultraviolet radiation. The floating gate is programmed when charge is stored in the floating gate. The cell is in an unprogrammed, or erased, state when the floating gate is discharged. Because of complex and time consuming procedures required to erase EPROMs, these devices have been used primarily in applications requiring read-only-memories.
Electrically programmable and electrically erasable read-only-memories (EEPROMs) were developed to provide the capability of electrically erasing programmed memory cells (see U.S. Pat. Nos. 4,203,138 and 4,099,196). Commercially available EEPROMs generally have used a thin oxide region to transfer the charge into and from a floating gate. In a typical memory, a two transistor cell is used. For instance, U.S. Pat. No. 4,203,158 discloses the fabrication of such an EEPROM cell. Further, U.S. Pat. No. 4,266,283 discloses the arrangement of EEPROMs into an array wherein X and Y select lines provide for the selection, programming and reading of various EEPROM cells. These EEPROM cells do not lend themselves to being reduced in substrate area as do the EPROM cells. Various techniques are disclosed to reduce the size of the memory array by providing higher-density cells. One such technique is disclosed in U.S. Pat. No. 4,432,075.
More recently, a new category of electrically erasable EPROMs/EEPROMs has emerged and these devices are sometimes referred to as "flash" EPROMs or flash EEPROMs. A general discussion of three types of cells used for these flash memories is described in Electronics Mar. 3, 1988 "High-Density Flash EEPROMs are About to Burst on the Market" by Robert Lineback. One type of flash memory uses a single device per cell and such cells are described in application Ser. No. 07/253,775 filed Oct. 5, 1988, entitled "Low Voltage EEPROM Cell" (assigned to the assignee of the present invention), which is a continuation application of patent application Ser. No. 892,446, filed Aug. 4, 1986, now abandoned. It is these types of cells that are used in conjunction with the present invention. Also see U.S. Pat. No. 4,868,619 and "A 256-k Bit Flash E.sup.2 PROM Using Triple-Polysilicon Technology", Masouka, et al., IEEE Journal of Solid-State Circuits, Vol SC-22, No. 4, August, 1987.
The single device per cell flash memory cells are programmed by the application of a positive potential (e.g., 4-7 V) to their drain region and a programming potential (e.g., 10-15 V) to their control gate. This causes electrons to be transferred onto the floating gate. During this time the source region is grounded. The cells are erased by application of a positive potential to the source region (e.g., 10-15 V) where the control gate is grounded and the drain region is left floating. This causes the electrons on the floating gate to tunnel through the gate oxide and into the channel and source region.
Care must be taken in erasing these cells to assure that the cell is not over-erased. That is, if too many electrons are removed from the floating gate, the floating gate may become positively charged and the cell will act as a depletion device. Such cells when coupled to a column line, can provide a path to ground even when the cell is not selected for reading and hence, prevent the reading of data from any of the cells along the column line.
As will be described in connection with FIG. 1, over erasing can be caused by a leakage current associated with the drain region of the cell. When this occurs, a "hot hole" erase results causing the cell to be over-erased. The present invention is directed towards compensating for this leakage; the present invention provides a circuit and method allowing cells exhibiting such leakage to be used.
U.S. Pat. No. 4,797,856 describes a method and apparatus for preventing an over-erase condition generally using a feedback arrangement. U.S. Pat. No. 4,860,261 describes a method for verifying drain leakage current.